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Thrilled to announce that @naveen_venk and I have joined @joinef to build @archgen_ .
Our thesis is simple:
The next generation of semiconductor design tools will not just automate workflows they will learn from every engineer who uses them.
Chip design today is full of repeated manual effort.
1. A senior physical design engineer fixes a timing issue.
2. Another engineer solves a congestion problem.
3. Someone else discovers a better macro placement strategy.
4. A team spends weeks tuning PPA across hundreds of experiments.
But most of this knowledge disappears into scripts, logs, webex threads, reports, and individual engineer's memory.
We鈥檙e changing that.
At @archgen_ , we鈥檙e building self-learning agents for semiconductor design, with specific focus on physical design.
Our agents work alongside engineers, run EDA flows, inspect reports, debug failures, optimize PPA, and capture the reasoning behind successful workflows.
1. When an engineer solves something, the agent learns.
2. When a strategy fails, the agent remembers why.
3. When a similar problem appears again, the agent can reuse the right approach.
Over time, this becomes an organisational memory layer for chip design. One that compounds.
Our vision is to make chip design feel less like manually stitching together fragmented tools and more like working with a team of expert agents that get better every day.
The future of semiconductor design is self-learning.
Huge thanks to @suhasasumukh 馃悙 and @localhosthq for being extremely generous with their credits and supporting us throughout.
#semiconductors #EDA #physicaldesign #ASIC #chipdesign #AIView quoted post on X
