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excited to partner with @youdotcom to serve kimi k3.1 pro on inference router from day 0
moonshot ai's latest open-weight model is now available with a 99.9% uptime sla from the you.com team and zero data retention.
try it today (link in thread)
moonshot ai's latest open-weight model is now available with a 99.9% uptime sla from the you.com team and zero data retention.
try it today (link in thread)
you.com You.com | Search and inference for AI The core AI infrastructure you need to maximize accuracy while reducing latency and costs. Kimi K3.1 Pro is live on Inference Router from day 0.
K3.1 is @Kimi_Moonshot's most capable open-weight model yet, with a 1M context window and a reported 65.7% on Terminal-Bench 4.0.
Run it in production with at least 99.9% uptime SLA, US hosting and ZDR available. No upfront commitment.View quoted post on X
wowza part 2
Wafer is now #3 on @OpenRouter in daily token volume!!View quoted post on X
wowza!
Took Wafer 4 months to get to 1 trillion tokens a day on @OpenRouter, but only 4 days to get to 2 trillion!View quoted post on X
if i had to learn cuda compilation, ptx, register spills, and gpu disassembly from scratch because my "optimized" kernel got slower, i'd start here
links in thread 🧵
the compilation and machine code section of our ai performance engineering repo contains four nvidia resources for understanding how cuda source becomes gpu instructions and inspecting the code behind ai kernels:
understanding ptx explains how nvcc separates cpu and gpu code, why ptx is a virtual instruction set, and how ptxas turns it into a cubin.
the article covers fatbins, driver jit compilation, and gpu compatibility, giving context for deployment targets and inference startup costs.
nvcc compiler driver covers gpu architecture targets, the files each compilation stage produces, separate compilation, and device linking.
the nvcc guide explains how to retain intermediate files and report register usage, shared memory, and spill loads and stores. those compiler reports help compare kernel builds after changes to tile size, unrolling, or fusion.
ptx isa defines register, local, shared, and global state spaces; memory ordering and synchronization; and arithmetic and matrix instructions.
ptx isa details operand layouts, data types, accumulation precision, and gpu requirements, plus completion rules for asynchronous copies. useful for checking data movement and numerical behavior in attention and matmul kernels.
cuda binary utilities covers extracting embedded ptx and cubins, disassembling native gpu instructions (sass), and reporting register counts and static memory usage with cuobjdump.
nvdisasm provides control-flow graphs when the cubin contains complete relocation information, plus register-liveness views.
with debug line information, nvdisasm can annotate instructions with source lines. useful for inspecting generated loads, stores, branches, and arithmetic after a kernel rewrite.
together, these resources connect the compilation process to the code being measured. they help identify what changed between kernel builds and what to investigate before the next correctness check or benchmark.
follow and save to keep up with the series.
links in thread 🧵
the compilation and machine code section of our ai performance engineering repo contains four nvidia resources for understanding how cuda source becomes gpu instructions and inspecting the code behind ai kernels:
understanding ptx explains how nvcc separates cpu and gpu code, why ptx is a virtual instruction set, and how ptxas turns it into a cubin.
the article covers fatbins, driver jit compilation, and gpu compatibility, giving context for deployment targets and inference startup costs.
nvcc compiler driver covers gpu architecture targets, the files each compilation stage produces, separate compilation, and device linking.
the nvcc guide explains how to retain intermediate files and report register usage, shared memory, and spill loads and stores. those compiler reports help compare kernel builds after changes to tile size, unrolling, or fusion.
ptx isa defines register, local, shared, and global state spaces; memory ordering and synchronization; and arithmetic and matrix instructions.
ptx isa details operand layouts, data types, accumulation precision, and gpu requirements, plus completion rules for asynchronous copies. useful for checking data movement and numerical behavior in attention and matmul kernels.
cuda binary utilities covers extracting embedded ptx and cubins, disassembling native gpu instructions (sass), and reporting register counts and static memory usage with cuobjdump.
nvdisasm provides control-flow graphs when the cubin contains complete relocation information, plus register-liveness views.
with debug line information, nvdisasm can annotate instructions with source lines. useful for inspecting generated loads, stores, branches, and arithmetic after a kernel rewrite.
together, these resources connect the compilation process to the code being measured. they help identify what changed between kernel builds and what to investigate before the next correctness check or benchmark.
follow and save to keep up with the series.
