Same Llama 3.1 70B model, same batch size, four chips. The decode speed ceiling moves entirely with memory bandwidth.
- H100 SXM5 (HBM3, 3.35 TB/s): about 24 tokens/sec
- H200 (HBM3e, 4.8 TB/s): about 34 tokens/sec
- B200 (8.0 TB/s): about 57 tokens/sec
- B300 (10.0 TB/s): about 71 tokens/sec
Vera Rubin's projected HBM4 (up to 22 TB/s) points to roughly 157 tokens/sec, about 6.5x the H100 ceiling. That figure is derived from NVIDIA's system-level spec, not a confirmed benchmark, and pricing isn't published yet.
- H100 SXM5 (HBM3, 3.35 TB/s): about 24 tokens/sec
- H200 (HBM3e, 4.8 TB/s): about 34 tokens/sec
- B200 (8.0 TB/s): about 57 tokens/sec
- B300 (10.0 TB/s): about 71 tokens/sec
Vera Rubin's projected HBM4 (up to 22 TB/s) points to roughly 157 tokens/sec, about 6.5x the H100 ceiling. That figure is derived from NVIDIA's system-level spec, not a confirmed benchmark, and pricing isn't published yet.